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PI74LVTC16245
3.3V 16-Bit Bi-Directional Transceiver with 3-State Outputs
Product Features
* Advanced low power CMOS design for 2.7V to 3.6V Vcc operation * Supports 5V input/output tolerance in mixed signal mode operation * Function compatible with LVT family of products * Balanced 24mA output drive * Typical VOLP (Output Ground Bounce) <0.8V at VCC=3.3V, TA=25C * Ioff and Power Up/Down 3-State support live insertion * Latch-up performance exceeds 200mA Per JESD78 * ESD protection exceeds JESD 22 - 2000V Human-Body Model (A114-B) - 200V Machine Model (A115-A) * Available Packages (Pb-free Available): - 48-pin 240-mil wide plastic TSSOP (A48) - 48-pin 300-mil wide plastic SSOP (V48) * Industrial Temperature -40C to +85C
Product Description
Pericom Semiconductor's PI74LVTC series of logic circuits are produced using the Company's advanced submicron CMOS technology, achieving industry leading speed. The PI74LVTC16245 is a non-inverting 16-bit Bidirectional Transceiver designed for low-voltage 2.7V to 3.6V VCC operation, with the capability of interfacing to the 5V system environment. This tranceiver is designed for asynchronous two-way communication between data buses. The direction control input pin (xDIR) determines the direction of the data flow through the bidirectional transceiver. The Direction and Output Enable controls are designed to operate this device as either two independent 8-bit tranceivers or one 16-bit transceiver. The output enable (xOE) input, when HIGH, disables both A and B ports by placing them in HIGH Z condition. When Vcc is between 0 to 1.5V during power up or power down, the outputs of the device are in the high-impedance state. To ensure the high-impedance state above1.5V, OE should be tied to Vcc through a pullup resistor; the minimum value of the resistor is determined by the current sinking capability of the driver. The device fully supports live-insertion with its Ioff and power-up/ down 3-state. The Ioff circuitry disables the outputs when the power is off, preventing the backflow of damaging current through the device. Power-up/down 3-state places the outputs in the high-impedance state during power up or power down, preventing driver conflict.
1 24
Logic Block Diagram
1DIR
48
2DIR 1OE 2A0
2 36 35 33 32 30 29 27 26 13 2B0 14 2B1 16 2B2 17 2B3 19 2B4 20 2B5 22 2B6 23 2B7 25 2OE 47 46 3 44 5 43 6 41 8 40 9 38 11 37 12
1A0 1A1 1A2 1A3 1A4 1A5 1A6 1A7
1B0 2A1 1B1 2A2 1B2 2A3 1B3 2A4 1B4 2A5 1B5 2A6 1B6 2A7 1B7
1
PS 8651A
05/19/03
Truth Table(4)
Inputs xOE L L H xDIR L H X Bus B Data to Bus A Bus A Data to Bus B Z Outputs
21098765432121098765432109876543210987654321210987654321098765432109876543212109876543210987654321098765432121098765432109876543210987654321 21098765432121098765432109876543210987654321210987654321098765432109876543212109876543210987654321098765432121098765432109876543210987654321
PI74LVTC16245 3.3V 16-Bit Bi-Directional Tranceivers with 3-State Outputs
Maximum Ratings
(Above which the useful life may be impaired. For user guidelines, not tested.) Supply voltage range, VCC .............................. -0.5V to +6.5V Input voltage range, VI(1) ................................. -0.5V to +6.5V Voltage range applied to any output in the high-impedance or power-off state, VO(1) ........ -0.5V to +6.5V Voltage range applied to any output in the active state, VO(1), (2) .................................. -0.5V to VCC +0.5V Input clamp current, IIK (VI <0) ..................................... -50mA Output clamp current, IOK (VO <0) ............................... -50mA Continous Output Current IO ....................................... 50mA Continous Current through each VCC or GND pin .............. 100mA Package thermal impedance, JA(3): package A ......... 104C/W package V ........... 94C/W Storage Temperature range, Tstg ..................... -65C to 150C Notes: Stresses greater than those listed under MAXIMUM RATINGS may cause permanent damage to the device. This is a stress rating only and functional operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect reliability. 1. Input negative-voltage and output voltage ratings may be exceeded if the input and output clamp current ratings are observed. 2. This value is limited to 6.5V maximum. 3. The package thermal impedance is calculated in accordance with JESD 51.
Product Pin Description
Pin Name xOE xDIR xAx xBx GND VC C De s cription 3- State Output Enable Inputs (Active LOW) Direction Control Input (Active HIGH) Side A Inputs or 3- State Outputs Side B Inputs or 3- State Outputs Ground Power
Product Pin Configuration
1DIR 1B0 1B1 GND 1B2 1B3 VCC 1B4 1B5 GND 1B6 1B7 2B0 2B1 GND 2B2 2B3 VCC 2B4 2B5 GND 2B6 2B7 2DIR 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 48 47 46 45 44 43 42 41 40 39 1OE 1A0 1A1 GND 1A2 1A3 VCC 1A4 1A5 GND 1A6 1A7 2A0 2A1 GND 2A2 2A3 VCC 2A4 2A5 GND 2A6 2A7 2OE
48-Pin 38 A, V 37
36 35 34 33 32 31 30 29 28 27 26 25
Notes: 4. H = High Signal Level L = Low Signal Level X = Don't Care or Irrelevant Z = High Impedance
2
PS 8651A
05/19/03
21098765432121098765432109876543210987654321210987654321098765432109876543212109876543210987654321098765432121098765432109876543210987654321 21098765432121098765432109876543210987654321210987654321098765432109876543212109876543210987654321098765432121098765432109876543210987654321
PI74LVTC16245 3.3V 16-Bit Bi-Directional Tranceivers with 3-State Outputs
Recommended Operating Conditions(5)
M in. VC C VIH VIL VI VO Supply Voltage High- level Input Voltage Low- level Input Voltage Input Voltage Output Voltage High or Low State 3- State VC C = 2.7V VC C = 3.0V to 3.6V VC C = 2.7V VC C = 3.0V to 3.6V Operating VC C = 2.7V to 3.6V VC C = 2.7V to 3.6V 0 0 0 2.7 2.0 0.8 5.5 VC C 5.5 - 12 - 24 12 24 10 15 0 - 40 +85 ns/V s/V C mA V M a x. 3.6 Units
IO H High- level output current IO L Low- level output current t/v Input transition rise or fall rate t/VC C Power- up ramp rate TA Operating free- air temperature
Notes: 5. All unused inputs must be held at VCC or GND to ensure proper device operation.
3
PS 8651A
05/19/03
21098765432121098765432109876543210987654321210987654321098765432109876543212109876543210987654321098765432121098765432109876543210987654321 21098765432121098765432109876543210987654321210987654321098765432109876543212109876543210987654321098765432121098765432109876543210987654321
PI74LVTC16245 3.3V 16-Bit Bi-Directional Tranceivers with 3-State Outputs
DC Electrical Characteristics (Over the Operating Range, TA = -40C to +85C)
Parame te rs VIK De s cription Clamp Diode Voltage VC C = 2.7V VC C = 2.7V to 3.6V VO H Output High Voltage VC C = 2.7V VC C = 3V VC C = 2.7V to 3.6V VO L Output Low Voltage VC C = 2.7V VC C = 3V Control Inputs II Input Leakage Current A or B Ports (6) Power Off Output Leakage Current Power- Up 3- State Current Power- Down 3- State Current Quiescent Power Supply Current Increase in IC C VC C = 3.6V VC C = 0V to 3.6V Te s t Conditions II = -18mA IO H = -100A IO H = -12mA IO H = -12mA IO H = -24mA IO L = 100A IO L = 12mA IO L = 12mA IO L = 24mA VI = 0V to 5.5V VI = 5.5V VI = VC C VI = GND IO F F IO ZP U IO ZP D IC C IC C VC C = 0V VC C = 0V to 1.5V VC C = 1.5V to 0V VCC = 2.7V to 3.6V VC C = 2.7V to 3.6V VI or VO = 0V to 5.5V VO = 0.5V to 5.5V, OE = don't care VO = 0.5V to 5.5V, OE = don't care VI = VC C or GND 3.6V VI 5.5V(7) One input at VC C - 0.6V(8), Other inputs at VC C or GND IO = 0 5 A 5 5 60 500 5 VC C -0.2V 2.2 2.4 2.2 0 .2 0.4 0.4 0.55 5 V M in. M a x. -1.2V Units
Notes: 6. For I/O ports, Input Leakage Current (II) includes the 3-state Output Leakage Current. Unused pins are at VCC or GND. 7. This applies in the disabled state only. 8. This is the increase in supply current for each input that is at the specified TTL voltage level rather than VCC or GND.
4
PS 8651A
05/19/03
21098765432121098765432109876543210987654321210987654321098765432109876543212109876543210987654321098765432121098765432109876543210987654321 21098765432121098765432109876543210987654321210987654321098765432109876543212109876543210987654321098765432121098765432109876543210987654321
PI74LVTC16245 3.3V 16-Bit Bi-Directional Tranceivers with 3-State Outputs
Capacitance
Parame te rs CI CIO C PD De s cription Control Input Capacitance Input/Output Capacitance Power Dissipation Capacitance (10) Te s t Conditions VCC = 3.3V, VI = VCC or GND VCC = 3.3V, VO = VCC or GND VCC = 3.3V, VI = 0V or VCC, f =10 MHz Typ.(9) 3.4 8 22 pF Units
Notes: 9. All typical values are measured at VCC = 3.3V, TA = 25C. 10. CPD is defined as the value of the internal equivalent capacitance which is derived from dynamic operating current consumption (ICCD) at no output loading and operating at 50% duty cycle, CPD is related to ICCD dynamic operating current by the expression: ICCD = (CPD)(VCC)(fIN)+(ICCstatic).
Switching Characteristics Over Operating Range
VCC = 3.3V 0.3V Parame te rs De s cription From (Input) To (Output) M in. tPLH tPHL tPZH tPZL tPHZ tPLZ tSK(O) Propagation Delay A or B B or A 1.0 1.0 1.0 1.0 1.0 1.0 CL = 50pF, RL = 500Ohm Typ.(11) 2.4 2.4 2.8 2.7 2.7 2.5 M ax. 3.5 3.5 4.9 4.9 4.3 4.3 0.5 VCC = 2.7V CL = 50pF, RL = 500Ohm M in. M a x. 3.9 3.9 5.3 5.3 4.8 4.8 ns Units
Output Enable Time
OE
A or B
Output Disable Time Output to Output Skew(12)
OE
A or B
Notes: 11. All typical values are measured at VCC = 3.3V, TA = 25C. 12. Skew between any two outputs, switching in the same direction.
5
PS 8651A
05/19/03
21098765432121098765432109876543210987654321210987654321098765432109876543212109876543210987654321098765432121098765432109876543210987654321 21098765432121098765432109876543210987654321210987654321098765432109876543212109876543210987654321098765432121098765432109876543210987654321
PI74LVTC16245 3.3V 16-Bit Bi-Directional Tranceivers with 3-State Outputs
PARAMETER MEASUREMENT INFORMATION VCC = 2.7V and 3.3V 0.3V
6V From Output Under Test
(See Note A)
500
S1
Open GND
Te s t tPLH/tPHL tPLZ/tPZL tPHZ/tPZH
S1 Open 6V GND
CL = 50pF
500
Load Circuit
tW 2.7V Input 1.5V 1.5V 0V
Voltage Waveforms Pulse Duration
Output Control (Low Level Enabling)
2.7V 1.5V tPZL 1.5V tPZH 1.5V tPLZ 3V VOL+0.3V tPHZ 1.5V VOH -0.3V VOL VOH 0V 0V
2.7V Input 1.5V tPLH 1.5V 1.5V 0V tPHL VOH Output 1.5V VOL
Output Waveform 1 S1 at 6V (see Note B)
Output Waveform 2 S1 at GND (see Note B)
Voltage Waveforms Propagation Delay Times
Voltage Waveforms Enable and Disable Times
Figure 1. Load Circuit and Voltage Waveforms
Notes: A. CL includes probe and jig capacitance. B. Waveform 1 is for an output with internal conditions such that the output is low except when disabled by the output control. Waveform 2 is for an output with internal conditions such that the output is high except when disabled by the output control. C. All input impulses are supplied by generators having the following characteristics: PRR 10 MHz, ZO = 50, tR 2.5ns, tF 2.5ns. D. The outputs are measured one at a time with one transition per measurement.
6
PS 8651A
05/19/03
21098765432121098765432109876543210987654321210987654321098765432109876543212109876543210987654321098765432121098765432109876543210987654321 21098765432121098765432109876543210987654321210987654321098765432109876543212109876543210987654321098765432121098765432109876543210987654321
PI74LVTC16245 3.3V 16-Bit Bi-Directional Tranceivers with 3-State Outputs
48-pin TSSOP (A) Package
48
.236 .244
6.0 6.2
1
.488 12.4 .496 12.6 .047 1.20 Max SEATING PLANE
.004 0.09 .008 0.20 0.45 .018 0.75 .030 .319 BSC 8.1
X.XX X.XX
DENOTES DIMENSIONS IN MILLIMETERS
.0197 BSC 0.50
.007 .010 0.17 0.27
.002 .006 0.05 0.15
48-pin SSOP (V) Package
48
.291 .299 7.39 7.59
.395 .420 10.03 10.67
Gauge Plane .010 0.25 1 .620 .630 15.75 16.00 .02 0.51 .04 1.01
.008 0.20 Nom.
.015 0.381 x 45 .025 0.635
.110 2.79 Max .025 BSC 0.635 X.XX DENOTES DIMENSIONS X.XX IN MILLIMETERS .008 0.20 .0135 0.34
0-8
.008 0.20 .016 0.40
7
PS 8651A
05/19/03
21098765432121098765432109876543210987654321210987654321098765432109876543212109876543210987654321098765432121098765432109876543210987654321 21098765432121098765432109876543210987654321210987654321098765432109876543212109876543210987654321098765432121098765432109876543210987654321
PI74LVTC16245 3.3V 16-Bit Bi-Directional Tranceivers with 3-State Outputs
Ordering Information
Orde ring Code PI74LVTC16245A PI74LVTC16245AE PI74LVTC16245V PI74LVTC16245VE Package Code A A V V Package Type 48- pin, 240- mil wide plastic TSSOP (A) Pb- free, 48- pin, 240- mil wide plastic TSSOP (A) 48- pin, 300- mil wide plastic SSOP (V) Pb- free, 48- pin, 300- mil wide plastic SSOP (V)
Notes: 1. Thermal characteristics can be found on the company web site at http://www.pericom.com/packaging/mechanicals.php 2. X = Tape/Reel
Pericom Semiconductor Corporation 2380 Bering Drive * San Jose, CA 95131 * 1-800-435-2336 * Fax (408) 435-1100 * http://www.pericom.com
8
PS 8651A 05/19/03

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